adc1613s NXP Semiconductors, adc1613s Datasheet - Page 18
adc1613s
Manufacturer Part Number
adc1613s
Description
Adc1613s Series Single 16-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Serial Jesd204a Interface
Manufacturer
NXP Semiconductors
Datasheet
1.ADC1613S.pdf
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ADC1613S_SER
Product data sheet
11.2.4 Biasing
11.3.1 Drive modes
11.3 Clock input
The common-mode input voltage (V
0.5V
The ADC1613S can be driven differentially (LVPECL). It can also be driven by a
single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to
ground via a capacitor).
Fig 15. Reference equivalent schematic
Fig 16. LVCMOS single-ended clock input
DDA
a. Rising edge LVCMOS
for optimal performance and should always be between 0.9 V and 2 V.
0.1 μF
clock input
1.5 V
VCM
LVCMOS
All information provided in this document is subject to legal disclaimers.
package
Rev. 1 — 14 March 2011
005aaa174
CLKM
CLKP
ESD
I(cm)
) on pins INP and INM should be set externally to
parasitics
Single 16-bit ADC; serial JESD204A interface
b. Falling edge LVCMOS
ADC1613S series
COMMON-MODE
REFERENCE
clock input
LVCMOS
ADC core
© NXP B.V. 2011. All rights reserved.
005aaa053
CLKM
CLKP
005aaa051
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