tda8026 NXP Semiconductors, tda8026 Datasheet - Page 18

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8026_1
Product data sheet
8.5.2.1 Bank 0 register (address: 48h) bit allocation
8.5.2.2 Bank 0 bit description
8.5.3.1 Bank 1 CSb[7:0] Register0 (address 40h) card slot 1 and card slot 2 bit allocation
8.5.2 Bank 0 register description
8.5.3 Bank 1 card slots 1 and 2 register descriptions
The device registers enable the microcontroller to control the TDA8026. The registers are
organized in bank pages to ensure compatibility with the TDA8023.
Bank 0 write register enables selection of the card slot number and access to the
corresponding registers in bank 1. The card slot registers in bank 1 are accessed using
the configuration byte (CSb[7:0]). The range 01h to 05h is used to select the specific card
slot starting at card slot 1 (01h) and ending with card slot 5 (05h) in a similar way to the
TDA8023 registers.
Table 8.
Table 9.
Table 10.
[1]
When at least one of the PRESL, SUPL, PROT, MUTE and EARLY bits is set to logic 1,
IRQN pin is driven LOW until the status byte has been read. After power-on, the SUPL bit
is set to logic 1 until the status byte has been read and the IRQN pin is LOW until the
voltage supervisor is deactivated.
Bit
Symbol
Access
Bit
7 to 0 CSb[7:0]
Bit
Card slot 1 (address 01h) and Card slot 2 (address 02h)
Symbol
Access
Symbol
Access
See
Symbol
Table 11
Bank 0 register (address: 48h) bit allocation
Bank 0 bit description
Bank 1 CSb[7:0] Register0 (address 40h) card slot 1 and
allocation
7
for the read mode bits and
All information provided in this document is subject to legal disclaimers.
Value
00h
01h
02h
03h
04h
05h
06h
VCC1V8
ACTIVE
[1]
[1]
7
W
R
Rev. 1 — 9 March 2010
6
Description
Bank 1 page selection:
selects product version and interrupts status register page
selects card slot 1 page
selects card slot 2 page
selects card slot 3 page
selects card slot 4 page
selects card slot 5 page
selects the clock frequency and I/O lines slew rate settings page
EARLY
I/OEN
W
R
6
5
Table 12
MUTE
W
R
5
REG[1:0]
4
for the write mode bits.
CSb[7:0]
PROT
R/W
W
R
4
Multiple smart card slot interface IC
3
PDWN
SUPL
W
R
3
CLKSW PRESL
5V/3VN
2
card slot
W
R
2
TDA8026
© NXP B.V. 2010. All rights reserved.
WARM
1
W
R
1
2 bit
START
PRES
18 of 59
0
W
R
0