tda8026 NXP Semiconductors, tda8026 Datasheet - Page 56

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
19. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Bank 1 CSb[7:0] Register0 (address 40h) card
Table 11. Bank 1 Register0 card slot 1 (address 01h) and
Table 12. Bank 1 Register0 card slot 1 (address 01h) and
Table 13. Bank 1 CSb[7:0] Register0 (address 42h) card
Table 14. Bank 1 Register1 (REG[1:0] = 00) card slot 1
Table 15. Bank 1 Register1 (REG[1:0] = 01) card slot 1
Table 16. Bank 1 Register1 (REG[1:0] = 01) card slot 1
Table 17. Bank 1 Register1 (REG[1:0] = 10) card slot 1
Table 18. Bank 1 Register1 (REG[1:0] = 10) card slot 1
Table 19. Bank 1 Register1 (REG[1:0] = 11) card slot 1
Table 20. Bank 1 Register1 (REG[1:0] = 11) card slot 1
Table 21. Bank 1 CSb[7:0] Register0 (address 40h) card
Table 22. Bank 1 Register0 card slot 3 (address 03h), card
Table 23. Bank 1 Register0 card slot 3 (address 03h), card
Table 24. Bank 1 CSb[7:0] Register1 (address 42h) card
Table 25. Bank 1 Register1 (REG[1:0] = 00) card slot 3
Table 26. Bank 1 Register1 (REG[1:0] = 01) card slot 3
TDA8026_1
Product data sheet
Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . .3
TDA8026 ball map . . . . . . . . . . . . . . . . . . . . . . .5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Base addressing . . . . . . . . . . . . . . . . . . . . . . .14
Write mode addresses . . . . . . . . . . . . . . . . . .14
Register overview . . . . . . . . . . . . . . . . . . . . . .16
Bank 0 register (address: 48h) bit allocation . .18
Bank 0 bit description . . . . . . . . . . . . . . . . . . .18
slot 1 and card slot 2 bit allocation . . . . . . . . . .18
card slot 2 (address 02h) read mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .19
card slot 2 (address 02h) write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .20
slots 1 and card slots 2 bit allocation . . . . . . . .21
(address 01h) and card slot 2 (address 02h)
Read/Write mode bit descriptions . . . . . . . . . .21
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
(address 01h) and card slot 2 (address 02h)
Read/Write mode bit descriptions . . . . . . . . . .23
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
(address 01h) and card slot 2 (address 02h)
Read/Write mode bit descriptions . . . . . . . . . .23
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . .23
slots 3 to 5 bit allocation . . . . . . . . . . . . . . . . .24
slot 4 (address 04h) and card slot 5
(address 05h) read mode bit descriptions . . . .24
slot 4 (address 04h) and card slot 5
(address 05h) write mode bit descriptions . . . .25
slots 3 and 5 bit allocation . . . . . . . . . . . . . . . .26
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode . . . . . . .26
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . .27
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
Table 27. Bank 1 Register1 (REG[1:0] = 01) card slot 3
Table 28. Bank 1 Register1 (REG[1:0] = 10) card slot 3
Table 29. Bank 1 Register1 (REG[1:0] = 10) card slot 3
Table 30. Bank 1 Register1 (REG[1:0] = 11) card slot 3
Table 31. Bank 1: Bank 1 Register1 (REG[1:0] = 11) card
Table 32. Asynchronous mode card clock settings . . . . . 29
Table 33. Synchronous mode card clock settings . . . . . . 29
Table 34. Bank 1 General registers (addresses: 40h, 42h;
Table 35. Bank 1 Product version register (address 40h;
Table 36. Bank 1 Interrupt register (address 42h;
Table 37. Bank 1 Slew rate register (address 40h;
Table 38. Clock Slew rate . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 39. I/O slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 40. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 41. Thermal characteristics . . . . . . . . . . . . . . . . . . 39
Table 42. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 43. Supply supervisor . . . . . . . . . . . . . . . . . . . . . . 40
Table 44. DC-to-DC converter . . . . . . . . . . . . . . . . . . . . 41
Table 45. Card drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 46. Sequencer and clock counter . . . . . . . . . . . . . 44
Table 47. Interface signals to microcontroller . . . . . . . . . 44
Table 48. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 49. SnPb eutectic process (from J-STD-020C) . . . 52
Table 50. Lead-free process (from J-STD-020C) . . . . . . 52
Table 51. Abbreviations and acronyms . . . . . . . . . . . . . . 53
Table 52. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 53
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . . 28
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . . 28
slot 3 (address 03h), card slot 4 (address 04h) and
card slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CSb[7:0] = 00h, 06h) bit allocation . . . . . . . . . 30
CSb[7:0] = 00h) read mode bit descriptions . . 30
CSb[7:0] = 00h) read mode bit descriptions . . 31
CSb[7:0] = 06h) read/write mode
bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 31
Multiple smart card slot interface IC
TDA8026
© NXP B.V. 2010. All rights reserved.
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