tda8026 NXP Semiconductors, tda8026 Datasheet - Page 27

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8026_1
Product data sheet
8.5.4.6 Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address
8.5.4.7 Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address
Table 25.
04h) and card slot 5 (address 05h) bit allocation
Table 26.
04h) and card slot 5 (address 05h) read/write mode bit descriptions
Table 27.
Bit
3 to 2
1 to 0
Bit
Symbol
Access
Bit
7 to 0
Symbol
CLKPD[1:0]
CLKDIV[1:0]
Symbol
D[7:0]
Bank 1 Register1 (REG[1:0] = 00) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode
Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) bit allocation
Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode bit descriptions
7
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Value Description
-
-
00
-
01
-
10
11
00
01
10
11
Rev. 1 — 9 March 2010
6
Description
programmable 8-bit clock counter. This value applies to all slots. The
reset value is AAh. See
35
asynchronous mode: when PWDN bit is set to logic 1, the
CLKPD[1] and CLKPD[2] bits define the card clock
synchronous mode: when the PWDN bit and the START bit are
set to logic 1, the CLKPD[2] bit remains logic 0 and the clock
frequency is controlled by the CLKPD[1] bit
asynchronous mode: the card clock =
Remark: (f
asynchronous mode: the card clock frequency (f
the CLKDIV[1:0] bits.
synchronous mode: the CLKDIV[1] and CLKDIV[2] bits are set to
logic 0 by the hardware
asynchronous mode: PWDN bit is logic 0, the CLKDIV[1] and
CLKDIV[2] bits define the card clock as follows:
f
f
f
f
clk(ext)
clk(ext)
clk(ext)
clk(ext)
asynchronous mode: the card clock is stopped and set to
logic 0
synchronous mode: the card clock is set to logic 0
asynchronous mode: the card clock is stopped and set to
logic 1
synchronous mode: the card clock is set to logic 1
5
on pin CLKIN2 for card slots 2 to 5
/ 2 on pin CLKIN2 for card slots 2 to 5
/ 4 on pin CLKIN2 for card slots 2 to 5
/ 5 on pin CLKIN2 for card slots 2 to 5
osc(int)
4
is the internal oscillator frequency)
Section 8.9 “Answer to reset counters” on page
D[7:0]
R/W
Multiple smart card slot interface IC
3
…continued
2
f
osc int
TDA8026
© NXP B.V. 2010. All rights reserved.
2
(clk)
1
) is set using
27 of 59
0