tda8026 NXP Semiconductors, tda8026 Datasheet - Page 36

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8026_1
Product data sheet
Fig 12. ATR counter timing check
WARM
RST
V
CLK
I/O
CC(n)
(n)
(n)
(n)
When operating, the microcontroller starts to configure the selected card slot (card supply
voltage) and then triggers the activation sequence using the START bit. The sequencer
then performs the activation sequence. The DC-to-DC converter is started, pin V
set to the previously configured card supply voltage, pin I/O
(see
The ATR counter dedicated to the card slot makes the following checks and takes the
steps required:
Figure 12
When the EARLY and MUTE bits are set to logic 1, they signal an interrupt (see the bit
descriptions in
•
•
•
•
•
•
200 CLK
cycles (I/O
ignored)
START bits from a card detected on pin I/O
ignored and the count continues.
START bits from a card detected while pin RST
clock cycles between 200 and the C[15:0] bits value (default 42100), cause the
EARLY and MUTE bits to be set to logic 1. Pin RST
microcontroller decides if it will accept the card.
START bits detected after the number of clock cycles is equal to the C[15:0] bits value
cause pin RST
START bits received from the card when the first number of clock cycles is equal to
the D[7:0] bits value (default 370) and pin RST
be set to logic 1.
Cards not answering before 42100 clock cycles (or the C[15:0] bits value) with RST
set to HIGH cause the MUTE bit to be set to logic 1.
Cards answering within the correct time frame, stops the clock cycles count and the
microcontroller can send commands to the card.
(EARLY and MUTE bits)
Section 8.8.2 on page 33
42100 CLK cycles
answer check
shows the timings checked by the ATR counters.
cold reset
Table 12 on page
All information provided in this document is subject to legal disclaimers.
(n)
370 CLK
cycles (early
answer check)
to be set to HIGH.
42100 CLK cycles
Rev. 1 — 9 March 2010
(mute check)
and
20,
Section 8.8.3 on page
Table 22 on page 24
200 CLK
cycles (I/O
ignored)
(EARLY and MUTE bits)
42100 CLK cycles
answer check
(n)
during the first 200 clock cycles are
(n)
Multiple smart card slot interface IC
(n)
set to HIGH cause the EARLY bit to
is set to LOW, with the number of
warm reset
(n)
34). Pin RST
and
remains LOW and the
(n)
370 CLK
cycles (early
answer check)
42100 CLK cycles
is enabled and CLK
Table 36 on page
(mute check)
TDA8026
(n)
© NXP B.V. 2010. All rights reserved.
is set to LOW.
001aal092
31).
CC(n)
(n)
36 of 59
starts
is
(n)