tda8026 NXP Semiconductors, tda8026 Datasheet - Page 21

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8026_1
Product data sheet
8.5.3.4 Bank 1 CSb[7:0] Register0 (address 42h) card slots 1 and card slot 2 bit allocation
8.5.3.5 Bank 1 Register1 (REG[1:0] = 00) card slot 1 (address 01h) and card slot 2
Table 13.
[1]
[2]
[3]
(address 02h) read/write mode bit descriptions
Table 14.
Bit
Card slot 1 (address 01h) and Card slot 2 (address 02h)
Card Slot 1 Reg[1:0] = 00; see
Symbol
Access
Card Slot 2 Reg[1:0] = 00; see
Symbol
Access
Card Slot 1 and card slot 2 Reg[1:0] = 01; see
Symbol
Access
Card Slot 1 and card slot 2 Reg[1:0] = 10; see
Symbol
Access
Card Slot 1 and card slot 2 Reg[1:0] = 11; see
Symbol
Access
Bit
7
6
5
4
Reserved bit position.
CLKPD[2] = bit 3 and CLKPD[1] = bit 2.
CLKDIV[2] = bit 2 and CLKDIV[1] = bit 1.
Symbol
CFGP2
RSTIN
C8(1)
C4(1)
Bank 1 CSb[7:0] Register0 (address 42h) card slots 1 and card slots 2 bit
allocation
Bank 1 Register1 (REG[1:0] = 00) card slot 1 (address 01h) and card slot 2
(address 02h) Read/Write mode bit descriptions
[2]
[2]
All information provided in this document is subject to legal disclaimers.
[1]
CFGP2
R/W
R/W
-
7
[1]
Value
1
0
1
0
-
-
-
-
Rev. 1 — 9 March 2010
RSTIN
RSTIN
Table 14 on page 21
Table 14 on page 21
R/W
R/W
Description
enables another type of card detection switch to be used on card
socket 1 and card socket 2
synchronous mode: when set to logic 1, pin RST
asynchronous mode: RSTIN is controlled by hardware (ATR
management)
set to logic 0: pin RST
writing C8(1) bit writes the corresponding value on C8
reading C8(1) bit reads the state of C8
writing C41 bit writes the corresponding value on C4
reading C41 bit reads the state of C4
6
if CFGP2 is logic 1, an interrupt is generated during each
power-up because the reset value of CFGP2 is logic level 0.
Refer to the Application note AN10724 for further information
the reset value of CFGP2 is logic 0. Refer to the Application
note AN10724 for further information
C8(1)
R/W
R/W
5
Table 16 on page 23
Table 18 on page 23
Table 20 on page 23
-
[1]
C4(1)
R/W
R/W
4
C[15:8]
D[7:0]
C[7:0]
(n)
R/W
R/W
R/W
Multiple smart card slot interface IC
is LOW
R/W
R/W
CLKPD[1:0]
CLKPD[1:0]
3
(1)
(1)
R/W
R/W
pin
2
[2]
[2]
pin
TDA8026
© NXP B.V. 2010. All rights reserved.
(n)
CLKDIV[1:0]
R/W
CLKDIV[1:0
R/W
1
is set to HIGH
(1)
(1)
pin
pin
R/W
R/W
21 of 59
0
[3]
[3]
]