uda1324ts NXP Semiconductors, uda1324ts Datasheet - Page 10

• Manufacturer Part Number: uda1324ts
• Description: Ultra Low-voltage Stereo Filter Dac
• Manufacturer: NXP Semiconductors

Philips Semiconductors
S
The system clock frequency is a 2-bit value to select the
external clock frequency.
Table 8 System clock settings
D
The data format is a 3-bit value to select the used data
format.
Table 9 Data input format settings
D
De-emphasis is a 2-bit value to enable the digital
de-emphasis filter.
Table 10 De-emphasis settings
2001 Mar 27
SC1
YSTEM CLOCK FREQUENCY
ATA FORMAT
E
IF2
DE1
Ultra low-voltage stereo filter DAC
0
0
1
1
0
0
0
0
1
1
1
1
-
EMPHASIS
0
0
1
1
SC0
IF1
0
1
0
1
0
0
1
1
0
0
1
1
DE0
0
1
0
1
512f
384f
256f
not used
IF0
0
1
0
1
0
1
0
1
no de-emphasis
de-emphasis, 32 kHz
de-emphasis, 44.1 kHz
de-emphasis, 48 kHz
s
s
s
I
LSB-justified 16 bits
LSB-justified 18 bits
LSB-justified 20 bits
MSB-justified
not used
not used
not used
2
S-bus
FUNCTION
FUNCTION
FORMAT
10
V
The volume control is a 6-bit value to program the volume
attenuation from 0 to 60 dB and
Table 11 Volume settings
M
Mute is a 1-bit value to enable the digital mute.
Table 12 Mute setting
VC5
OLUME CONTROL
UTE
MT
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
:
0
1
VC4
no muting
muting
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
:
VC3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
:
VC2
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
:
FUNCTION
VC1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
:
VC0 VOLUME (dB)
UDA1324TS
Product specification
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
:
dB in steps of 1 dB.
51
0
0
52
54
57
60
:
1
2