dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 385

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

ASLL.L
Operation:
If S[15] = 0 or S is not a register,
D << S →
Else
D >> –S → D
Description: Arithmetically shift the second operand to the left by the value contained in the 5 lowest bits of the first
Example:
Explanation of Example:
Condition Codes Affected:
Freescale Semiconductor
Before Execution
A2
0
D
operand (or by an immediate integer). Store the result back in the destination (D) with zeros shifted
into the LSB. The shift count can be a 5-bit positive immediate integer or the value contained in X0,
Y0, Y1, or the MSP of an accumulator. For 36- and 32-bit destinations, the MSP:LSP are shifted with
sign extension from bit 31 (the FF2 portion is ignored). If the shift count in a register is negative (bit
15 is set), the direction of the shift is reversed, maintaining sign integrity. The result is not affected by
the state of the saturation bit (SA).
ASLL.L Y0,A
Prior to execution, the A accumulator contains the value to be shifted ($0123:4567), and the Y0 regis-
ter contains the amount by which to shift ($04). The ASLL.L instruction arithmetically shifts the value
$0123:4567 by 4 bits to the left and places the result in the destination register A. Since the destination
is an accumulator, the extension word (A2) is filled with sign extension.
N
Z
LF
15
— Set if MSB of result is set
— Set if result equals zero
(no parallel move)
(no parallel move)
0123
2000
A1
Y1
P4
14
13
P3
Multi-Bit Arithmetic Left Shift Long
SR
P2
12
MR
P1
11
; shift A left by amount in Y0 and store in A
0300
4567
0024
A0
Y0
P0
10
Instruction Set Details
I1
9
Assembler Syntax:
ASLL.L
ASLL.L
I0
8
SZ
7
After Execution
A2
6
L
0
5
E
S,D
S,D
U
4
1234
2000
CCR
A1
Y1
N
3
SR
2
Z
V
(no parallel move)
(no parallel move)
1
0300
5670
0024
A0
Y0
C
0
ASLL.L
A-41