dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 6
dsp56800e
Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800E.pdf
(706 pages)
- Current page: 6 of 706
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Chapter 5
Data Arithmetic Logic Unit
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.3
5.3.1
5.3.2
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.4
5.3.4.1
5.3.4.2
5.3.4.3
5.3.4.4
5.3.5
5.3.6
5.3.6.1
5.3.6.2
5.3.6.3
5.3.6.4
5.4
5.4.1
5.4.2
5.5
5.5.1
5.5.2
5.5.3
5.5.3.1
5.5.3.2
5.5.3.3
vi
Data ALU Overview and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Accessing the Accumulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Fractional and Integer Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Unsigned Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Extended- and Multi-Precision Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Data Registers (X0, Y1, Y0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Accumulator Registers (A, B, C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Multiply-Accumulator (MAC) and Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Single-Bit Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Arithmetic and Logical Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Data Limiter and MAC Output Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Accessing an Entire Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Accessing Portions of an Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Reading and Writing Integer Data to an Accumulator . . . . . . . . . . . . . . . . . . . . . . 5-12
Reading 16-Bit Results of DSC Algorithms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Converting a 36-Bit Accumulator to a 16-Bit Value . . . . . . . . . . . . . . . . . . . . . . . 5-13
Saving and Restoring Accumulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Bit-Manipulation Operations on Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
DSP56800E Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Shifting Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Condition Codes for Unsigned Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Unsigned Single-Precision Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Extended-Precision Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Multi-Precision Fractional Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Multi-Precision Integer Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
Writing an Accumulator with a Small Operand . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Using the Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Fractional Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Integer Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Operand Re-Ordering for Multiplication Instructions . . . . . . . . . . . . . . . . . . . 5-20
General-Purpose Four-Quadrant Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Positive Dividend and Divisor with Remainder . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Signed Dividend and Divisor with No Remainder . . . . . . . . . . . . . . . . . . . . . . 5-23
Division Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Shifting 16-Bit Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Shifting with Accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Signed 32-Bit × Signed 32-Bit with 32-Bit Result . . . . . . . . . . . . . . . . . . . . . . 5-33
Unsigned 32-Bit × Unsigned 32-Bit with 32-Bit Result. . . . . . . . . . . . . . . . . . 5-34
Signed 32-Bit × Signed 32-Bit with 64-Bit Result . . . . . . . . . . . . . . . . . . . . . . 5-34
Shifting 32-Bit Long Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Shifting Accumulators by 16 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
DSP56800E Core Reference Manual
Freescale Semiconductor
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