dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 46

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Core Architecture Overview
An instruction fetch will take place on every clock cycle, although it is possible for data memory accesses
to be performed without an instruction fetch. Such accesses typically occur when a hardware loop is
executed and the repeated instruction is only fetched on the first loop iteration. See Section 8.5, “Hardware
Looping,” on page 8-18 for more information on hardware loops.
2.4.4
The data arithmetic logic unit (ALU) performs all of the arithmetic, logical, and shifting operations on data
operands. The data ALU contains the following components:
All in a single instruction cycle, the data ALU can perform multiplication, multiply-accumulation (with
positive or negative accumulation), addition, subtraction, shifting, and logical operations. Division and
normalization operations are provided by iteration instructions. Signed and unsigned multi-precision
arithmetic is also supported. All operations are performed using two’s-complement fractional or integer
arithmetic.
Data ALU source operands can be 8, 16, 32, or 36 bits in size and can be located in memory, in immediate
instruction data, or in the data ALU registers. Arithmetic operations and shifts can have 16-, 32-, or 36-bit
results. The instruction set also supports 8-bit results for some arithmetic operations. Logical operations
are performed on 16- or 32-bit operands and yield results of the same size. The results of data ALU
operations are stored either in one of the data ALU registers or directly in memory.
Chapter 5, “Data Arithmetic Logic Unit,” contains a detailed description of the data ALU.
2.4.5
The address generation unit (AGU) performs all of the calculations of effective addresses for data operands
in memory. It contains two address ALUs, allowing up to two 24-bit addresses to be generated every
instruction cycle: one for either the primary data address bus (XAB1) or the program address bus (PAB),
and one for the secondary data address bus (XAB2). The address ALU can perform both linear and modulo
address arithmetic. The AGU operates independently of the other core units, minimizing
address-calculation overhead.
The AGU can directly address 2
words on the PAB. The XAB1 bus can address byte, word, and long data operands. The PAB and XAB2
buses can only address words in memory.
The AGU consists of the following registers and functional units:
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One instruction fetch and one write to data memory
One instruction fetch and two reads from data memory
Three 16-bit data registers (X0, Y0, and Y1)
Four 36-bit accumulator registers (A, B, C, and D)
One multiply-accumulator (MAC) unit
A single-bit accumulator shifter
One arithmetic and logical multi-bit shifter
One MAC output limiter
One data limiter
Seven 24-bit address registers (R0–R5 and N)
Four shadow registers (for R0, R1, N, and M01)
Data Arithmetic Logic Unit (ALU)
Address Generation Unit (AGU)
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DSP56800E Core Reference Manual
(16M) words on the XAB1 and XAB2 buses. It can access 2
Freescale Semiconductor
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(2M)