dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 43
dsp56800e
Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800E.pdf
(706 pages)
- Current page: 43 of 706
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2.4
The DSP56800E system architecture encompasses all the on-chip components, including the core, on-chip
memory, peripherals, and the buses that are necessary to connect them. Figure 2-3 shows the overall
system architecture for a device with an external bus.
The complete architecture includes the following components:
Some DSP56800E devices might not implement an external bus interface. Regardless of the
implementation, all peripherals communicate with the DSP56800E core via the IP-BUS interface. The
IP-BUS–interface standard connects the two data address buses and the CDBR, CDBW, and XDB2
uni-directional data buses to the corresponding bus interfaces on the peripheral devices. The program
memory buses are not connected to peripherals.
Freescale Semiconductor
•
•
•
•
•
•
IP-BUS
DSP56800E core
On-chip program memory
On-chip data memory
On-chip peripherals
Freescale IP-BUS peripheral interface
External bus interface
System Architecture and Peripheral Interface
DSP56800E
Core
Figure 2-3. DSP56800E Chip Architecture with External Bus
Peripheral
PAB
PDB
XAB1
CDBR
CDBW
XAB2
XDB2
Program
Memory
Core Architecture Overview
Peripheral
Memory
Data
System Architecture and Peripheral Interface
Peripheral
Interface
Interface
External
IP-BUS
Bus
External
Address
External
Data
2-5
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