ep1s25 Altera Corporation, ep1s25 Datasheet - Page 137
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ep1s25
Manufacturer Part Number
ep1s25
Description
Stratix Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1S25.pdf
(276 pages)
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Altera Corporation
July 2005
Notes to
(1)
(2)
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVDS
LVPECL
3.3-V PCML
HyperTransport
Differential HSTL
Differential SSTL
GTL
GTL+
1.5-V HSTL Class I and II
1.8-V HSTL Class I and II
SSTL-18 Class I and II
SSTL-2 Class I and II
SSTL-3 Class I and II
AGP (1× and 2
CTT
Table 2–31. Stratix Supported I/O Standards
This I/O standard is only available on input and output clock pins.
This I/O standard is only available on output column clock pins.
I/O Standard
Table
2–31:
°
)
(2)
(1)
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
■
■
■
■
■
Table 2–31
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Differential
Differential
Differential
Differential
Differential
Differential
1.8-V HSTL Class I and II
SSTL-3 Class I and II
SSTL-2 Class I and II
SSTL-18 Class I and II
CTT
Type
describes the I/O standards supported by Stratix devices.
Input Reference
Voltage (V
0.75
1.25
0.75
0.90
1.25
1.32
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(V)
0.8
1.0
0.9
1.5
1.5
REF
)
Voltage (V
Stratix Device Handbook, Volume 1
Output Supply
N/A
N/A
(V)
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
3.3
3.3
2.5
1.5
2.5
1.5
1.8
1.8
2.5
3.3
3.3
3.3
CCIO
)
Stratix Architecture
Voltage (V
Termination
Board
0.75
1.25
1.20
0.75
0.90
1.25
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(V)
1.5
0.9
1.5
1.5
2–123
TT
)