ep1s25 Altera Corporation, ep1s25 Datasheet - Page 68
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ep1s25
Manufacturer Part Number
ep1s25
Description
Stratix Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1S25.pdf
(276 pages)
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Digital Signal Processing Block
2–54
Stratix Device Handbook, Volume 1
Table 2–13
DSP block multipliers can optionally feed an adder/subtractor or
accumulator within the block depending on the configuration. This
makes routing to LEs easier, saves LE routing resources, and increases
performance, because all connections and blocks are within the DSP
block. Additionally, the DSP block input registers can efficiently
implement shift registers for FIR filter applications.
Figure 2–30
18 × 18-bit multiplier mode.
configuration of the DSP block.
Notes to
(1)
(2)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Table 2–13. DSP Blocks in Stratix Devices
Device
Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
The number of supported multiply functions shown is based on signed/signed
or unsigned/unsigned implementations.
Table
shows the number of DSP blocks in each Stratix device.
shows the top-level diagram of the DSP block configured for
2–13:
DSP Blocks
10
10
12
14
18
22
6
Figure 2–31
Multipliers
Total 9 × 9
112
144
176
48
80
80
96
shows the 9 × 9-bit multiplier
Notes
Total 18 × 18
Multipliers
(1),
24
40
40
48
56
72
88
(2)
Altera Corporation
Total 36 × 36
Multipliers
July 2005
10
10
12
14
18
22
6