ep1s25 Altera Corporation, ep1s25 Datasheet - Page 86

• Manufacturer Part Number: ep1s25
• Description: Stratix Device Family Data Sheet
• Manufacturer: Altera Corporation

Digital Signal Processing Block
Figure 2–41. DSP Block Interface to Interconnect
2–72
Stratix Device Handbook, Volume 1
C4 and C8
Interconnects
LAB
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
10
A bus of 18 control signals feeds the entire DSP block. These signals
include clock[0..3] clocks, aclr[0..3] asynchronous clears,
ena[1..4] clock enables, signa, signb signed/unsigned control
signals, addnsub1 and addnsub3 addition and subtraction control
signals, and accum_sload[0..1] accumulator synchronous loads. The
Row Interface
18
3
Block
18 Inputs per Row
R4 and R8 Interconnects
10
9
Control
[17..0]
DSP Block
Row Structure
[17..0]
18 Outputs per Row
Nine Direct Link Outputs
to Adjacent LABs
18
18
9
Altera Corporation
Direct Link Interconnect
from Adjacent LAB
July 2005
LAB