ep1s25 Altera Corporation, ep1s25 Datasheet - Page 253
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ep1s25
Manufacturer Part Number
ep1s25
Description
Stratix Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1S25.pdf
(276 pages)
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Altera Corporation
January 2006
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
LVPECL
PCML
LVDS
HyperTransport
technology
Table 4–121. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1,
2, 3, 4] Pins in Flip-Chip Packages
I/O Standard
(2)
(2)
(2)
(2)
-5 Speed
Grade
400
400
400
350
400
200
200
167
167
150
150
150
150
250
225
250
225
250
225
400
400
400
300
717
420
717
420
-6 Speed
Grade
350
350
350
300
350
167
167
150
150
133
133
133
133
225
225
225
225
225
225
350
350
350
250
717
420
717
420
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
-7 Speed
Grade
300
300
300
300
300
125
125
133
133
133
133
133
133
200
200
200
200
200
300
300
300
200
500
420
500
420
200
-8 Speed
Grade
300
300
300
300
300
125
125
133
133
133
133
133
133
200
200
200
200
200
200
300
300
300
200
500
420
500
420
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
4–83
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