ep1s25 Altera Corporation, ep1s25 Datasheet - Page 237
![no-image](/images/manufacturer_photos/0/0/41/altera_corporation_sml.jpg)
ep1s25
Manufacturer Part Number
ep1s25
Description
Stratix Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1S25.pdf
(276 pages)
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Altera Corporation
January 2006
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL+
CTT
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.8-V HSTL Class I
LVDS
LVPECL
3.3-V PCML
HyperTransport
Table 4–104. Stratix I/O Standard Row Pin Input Delay Adders
Parameter
-5 Speed Grade
Min
–152
–168
–193
–193
–262
–262
–105
–151
–126
–149
–149
Max
181
300
–65
21
77
0
0
0
-6 Speed Grade
Min
–160
–177
–203
–203
–276
–276
–111
–159
–133
–157
–157
Max
190
315
–69
–81
22
0
0
0
-7 Speed Grade
Min
Stratix Device Handbook, Volume 1
–184
–203
–234
–234
–317
–317
–127
–183
–153
–180
–180
Max
218
362
–79
–93
DC & Switching Characteristics
25
0
0
0
-8 Speed Grade
Min
–216
–239
–275
–275
–373
–373
–150
–215
–179
–212
–212
–110
Max
257
426
–93
29
0
0
0
Unit
4–67
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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