xc3s1400an Xilinx Corp., xc3s1400an Datasheet - Page 6

• Manufacturer Part Number: xc3s1400an
• Description: Spartan-3an Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Introduction and Ordering Information
•
•
•
•
•
Table 3: Available User I/Os and Differential (Diff) I/O Pairs
6
Notes:
1.
2.
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Sector-based data protection and security features
♦
♦
128-byte Security Register
♦
♦
♦
100,000 Program/Erase cycles
20-year data retention
Comprehensive programming support
♦
♦
♦
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The Diff input-only pin count includes dedicated inputs and differential pins on banks restricted to inputs. The differential
(Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are
restricted to differential inputs.
Each Spartan-3AN FPGA has a pin-compatible Spartan-3A FPGA equivalent, although Spartan-3A FPGAs do not have internal SPI Flash.
Device
Sector Protect: Write- and erase-protect a sector
(changeable)
Sector Lockdown: Sector data is unchangeable
(permanent)
Separate from FPGA’s unique Device DNA
identifier
64-byte factory-programmed identifier unique to
the in-system Flash memory
64-byte one-time programmable,
user-programmable field
In-system prototype programming via JTAG using
Xilinx
or later software
Product programming support using BPM
Microsystems programmers with appropriate
programming adapter
Design examples demonstrating in-system
programming from a Spartan-3AN FPGA
application
Platform Cable USB
User
108
(7)
–
–
–
–
TQG144
and iMPACT ISE 9.1.02i
(24)
Diff
50
–
–
–
–
User
(35)
195
–
–
–
–
FTG256
www.xilinx.com
Diff
(50)
90
–
–
–
–
I/O Capabilities
The Spartan-3AN FPGA SelectIO interface supports many
popular single-ended and differential standards.
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional,
input-only pins as indicated in
Spartan-3AN FPGAs support the following single-ended
standards:
•
•
•
•
•
Spartan-3AN FPGAs support the following differential
standards:
•
•
•
•
•
User
311
(63)
–
–
–
–
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
FGG400
(78)
Diff
142
–
–
–
–
User
(84)
372
–
–
–
–
FGG484
Table
Diff
165
(93)
DS557-1 (v3.1) June 2, 2008
–
–
–
–
3.
Product Specification
User
(94)
502
–
–
–
–
FGG676
Table 3
(131)
Diff
227
–
–
–
–
R