xc3s1400an Xilinx Corp., xc3s1400an Datasheet - Page 73

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xc3s1400an

Manufacturer Part Number
xc3s1400an
Description
Spartan-3an Fpga Family Data Sheet
Manufacturer
Xilinx Corp.
Datasheet

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User I/Os by Bank
Table 67
distributed between the four I/O banks on the TQG144
package. The AWAKE pin is counted as a Dual-Purpose
I/O.
Table 67: User I/Os Per Bank for the XC3S50AN in the TQG144 Package
Footprint Migration Differences
The XC3S50AN FPGA is the only Spartan-3AN device
offered in the TQG144 package.
The XC3S50AN FPGA is pin compatible with the
Spartan-3A XC3S50A FPGA in the TQ(G)144 package,
although the Spartan-3A FPGA requires an external
configuration source.
DS557-4 (v3.1) June 2, 2008
Product Specification
Top
Right
Bottom
Left
TOTAL
Package
Edge
indicates how the 108 available user-I/O pins are
R
I/O Bank
0
1
2
3
Maximum I/O
108
27
25
30
26
I/O
14
11
15
42
2
www.xilinx.com
INPUT
1
0
0
1
2
All Possible I/O Pins by Type
DUAL
21
26
1
4
0
VREF
3
2
1
2
8
Pinout Descriptions
CLK
30
8
8
6
8
73

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