pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 235

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Registers
All IDE device registers are defined in the ATA-2 Specification. These registers can be
accessed directly from PI or indirectly via GPXIO registers. The lower five bits of the
GPXIO address register need to be configured as follows:
Table 4: GPXIO Address Configuration
Programming IDE Registers
IDE is a submodule of Document title variable. It shares PCI pins with other XIO
blocks. Three XIO SEL pins can be configured for use by any XIO device. Each SEL
pin is associated with the profile register in the PCI block. The profile register
determines the mode of the SEL pin, pulse width for control signals and memory
apertures for each mode.
Before accessing any IDE register, the appropriate profile register needs to be
programmed. For example, if XIO_SEL[1] has been used for IDE, the sel1_profile
register needs to be programmed and IDE needs to be enabled.
Address to be
Written
5’b40
5’b44
5’b48
5’b4C
5’b50
5’b54
5’b58
5’b5C
5’b38
•
•
•
•
•
•
•
•
At power on, the IDE disk will respond in PIO-0 mode only.
Program the appropriate register in PIO-0 mode to set PIO-4 mode.
Using sel1_profile register, set lo and high period of DIOR/DIOW pulses for PIO-4
mode.
High period in selx_profile register is used for the setup time of DA/CS lines with
DIOR/DIOW.
Low period in selx_profile register is used for the lo period of the DIOR/DIOW
pulse.
Hold of DA/CS with respect to DIOR/DIOW is always for one PCI clock.
Recommended values for sel_we_hi and sel_we_lo for PIO-0 mode are 7 and 13,
respectively (assuming a 33 MHz PCI clock).
Recommended values for sel_we_hi and sel_we_lo for PIO-4 mode are 1 and 3
respectively.
Register Name
Data register
ERR/Feature
Sector count
Sector number
Cylinder Low
Cylinder High
Device/Head
Status/Command
Alternate status/Device
control
Rev. 3 — 17 March 2006
Address on IDE
CS1
1
1
1
1
1
1
1
1
0
CS0
0
0
0
0
0
0
0
0
1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX15xx Series
DA2
0
0
0
0
1
1
1
1
1
DA1
0
0
1
1
0
0
1
1
1
DA0
0
1
0
1
0
1
0
1
0
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