pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 814

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
6.5 DTL-to-MTL Adapters
6.6 PCI Interface
The DTL-to-MTL adaptor translates DTL-Bus initiated read and write transactions to
MTL Memory transactions. The DTL interface can either be an address invariant (See
Section 6.2.2 on page
page
For DTL interfaces that are address invariant, the translation is performed in a byte-
address invariant way, i.e. the byte address associated with every 8-bit quantity must
be equal on each side of the bridge. Note that this translation need not be aware of
the unit size being transported. The module that was the originator of units has
performed swapping and packing such that each byte has been given the correct byte
address.
For DTL interfaces that follow DTL data ordering rules, the translation takes into
account the data unit size on the DTL and the system endian mode, and converts the
data into an address invariant view on the MTL interface. The Module that was the
originator of units need not perform swapping and packing such that each byte has
been given the correct byte address (The IP need not be aware of the System
Endianmode signal).
The translation occurs in two steps. When writing data to memory, the first step flips
the 32-bit DTL-Bus writes to a 32-bit address invariant view (depending on endian
mode and unit data size). The second step performs packing from this 32-bit
address-invariant data to the 64-bit MTL Memory Bus. For modules that read memory
data, the two steps occur in the reverse direction.
The MTL-Bus associates addresses with each byte transferred, depending on the
DTL-Bus unit data size and the setting of the big-endian signal. This byte address is
given in
address wires.
The DTL interface can either follow the address invariance rules (as indicated in
Table
The PCI interface on the PNX15xx Series connects to the off-chip PCI-bus, the DCS
Network and the MTL Memory Bus. As with any bridge, the PCI interface must
maintain the byte address of any byte of a transaction on all sides of the bridge.
The PCI interface bridges the following transactions in the PNX15xx Series:
•
•
•
•
PCI master read/writes from/to PNX15xx Series MMIO registers using 32-bit
transactions only
PCI master read/writes from/to PNX15xx Series SDRAM
DCS Network Master initiated read/writes from/to PCI targets
PCI interface internal DMA transactions, where the source can be a PCI target or
DRAM, and the destination is a PCI target or DRAM.
29-11).
7) or follow DTL Data ordering rules (as indicated in
Table
8, where the value “A” denotes the integer value on PI-Bus A[n:2]
Rev. 3 — 17 March 2006
29-12) or follow DTL data ordering rules (See
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 29: Endian Mode
Table
5).
Section 6.2.1 on
29-14