pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 248

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 8: Registers Description
PNX15XX_SER_3
Product data sheet
Bit
3
2:0
Offset 0x04 0058
31:4
3
2:0
Offset 0x04 006C
This register must be initialized before any PCI cycles will be entertained. The boot loader is expected to load the values at
boot time. This register is a Write-once/Read-only register (R/W1).
31:16
15:0
Offset 0x04 0074
31:8
7:0
Offset 0x04 007C
31:24
23:16
15:8
7:0
Offset 0x04 0080
31:27
26
25
24:19
18:16
15:8
7:0
Offset 0x04 0084
31:1
1:0
Symbol
Prefetchable
Type
Base Address 18
Prefetchable
Type
subsystem ID
subsystem vendor ID
Reserved
CAP_PTR
max_lat
min_gnt
interrupt pin
Interrupt Line
Reserved
d2_support
d1_support
Reserved
version
Next Item Pointer
Cap_ID
Reserved
pwr_state
Base Address 18 Image
Subsystem ID/Subsystem Vendor ID Write Port
Image of Configuration Reg 34
Image of Configuration Reg 3C
Image of Configuration Reg 40
Image of Configuration Reg 44
Acces
s
R
R
R/W*
R
R
R/W1
R/W1
R
R
R/W1
R/W1
R
R/W*
R
R
R
R
R
R
R
R
R/W*
Value
cfg*
0
1C00000 PCI configuration Base address for XIO.
cfg*
0
0
0
0
40
0x18
0x09
0x01
0x00
00000
cfg*
cfg*
0
010
00
01
0
0
Rev. 3 — 17 March 2006
Description
*Value is determined at boot time by pci_setup register.
Indicates type 0 memory space (locatable anywhere in 32-bit
address space).
This register affects the decode and routing of the bus controllers. It
should not be relied on as stable for 10 clocks after writing.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
*Value is determined at boot time by pci_setup register.
Indicates PCI “type 0” memory space (locatable anywhere in 32-bit
address space).
This is the write port for the Subsystem ID (PCI config 2C).
This is the write port for the Subsystem Vendor ID (PCI config 2C).
Capabilities Pointer
Max Latency
Minimum Grant
Interrupt pin information
This register conveys interrupt line routing information.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
1 = Device supports D2 power management state.
*Value is determined by pci_setup register.
1 = Device supports D1 power management state.
*Value is determined by pci_setup register.
Indicates compliance with version 1.1 of PM.
There are no other extended capabilities.
Indicates this is power management data structure.
Power State
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX15xx Series
7-29