mc68hc912d60c Freescale Semiconductor, Inc, mc68hc912d60c Datasheet - Page 277

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mc68hc912d60c

Manufacturer Part Number
mc68hc912d60c
Description
Hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
SP0BR SPI BAUD RATE REGISTER
÷
2
÷
4
INTERRUPT
REQUEST
÷
SPI
8
(SAME AS E RATE)
MCU P CLOCK
÷
16
DIVIDER
SELECT
÷
Figure 15-3. Serial Peripheral Interface Block Diagram
32
SP0SR SPI STATUS REGISTER
SPI CONTROL
÷
64
A clock phase control bit (CPHA) and a clock polarity control bit (CPOL)
in the SP0CR1 register select one of four possible clock formats to be
used by the SPI system. The CPOL bit simply selects non-inverted or
inverted clock. The CPHA bit is used to accommodate two
fundamentally different protocols by shifting the clock by one half cycle
or no phase shift.
÷
128
÷
256
Multiple Serial Interface
SP0DR SPI DATA REGISTER
SHIFT CONTROL LOGIC
8-BIT SHIFT REGISTER
READ DATA BUFFER
INTERNAL BUS
MSTR
SPE
SP0CR1 SPI CONTROL REGISTER 1
CLOCK
LOGIC
CLOCK
SWOM
LSBF
SP0CR2 SPI CONTROL REGISTER 2
Serial Peripheral Interface (SPI)
CONTROL
S
M
M
S
S
M
LOGIC
PIN
Multiple Serial Interface
MISO
MOSI
SCK
PS7
PS4
PS5
PS6
SS
Technical Data
277

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