mc68hc912d60c Freescale Semiconductor, Inc, mc68hc912d60c Datasheet - Page 283

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mc68hc912d60c

Manufacturer Part Number
mc68hc912d60c
Description
Hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
SP0BR — SPI Baud Rate Register
SP0SR — SPI Status Register
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
RESET:
SPIF
Bit 7
Bit 7
0
0
0
WCOL
6
0
6
0
0
Read anytime. Write anytime.
At reset, E Clock divided by 2 is selected.
SPR[2:0] — SPI Clock (SCK) Rate Select Bits
Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
These bits are used to specify the SPI clock rate.
SPIF is set after the eighth SCK cycle in a data transfer and it is
cleared by reading the SP0SR register (with SPIF set) followed by an
access (read or write) to the SPI data register.
SPR2
0
0
0
0
1
1
1
1
5
0
0
5
0
0
SPR1
0
0
1
1
0
0
1
1
Multiple Serial Interface
Table 15-4. SPI Clock Rate Selection
MODF
4
0
4
0
0
SPR0
0
1
0
1
0
1
0
1
3
0
0
3
0
0
E Clock
Divisor
128
256
16
32
64
2
4
8
SPR2
2
0
2
0
0
E Clock = 4 MHz
Frequency at
62.5 kHz
31.3 kHz
15.6 kHz
2.0 MHz
1.0 MHz
500 kHz
250 kHz
125 kHz
Serial Peripheral Interface (SPI)
SPR1
1
0
1
0
0
Multiple Serial Interface
E Clock = 8 MHz
Frequency at
SPR0
Bit 0
Bit 0
62.5 KHz
31.3 KHz
500 KHz
250 KHz
125 KHz
4.0 MHz
2.0 MHz
1.0 MHz
0
0
0
Technical Data
$00D2
$00D3
283

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