mc68hc08az60 Freescale Semiconductor, Inc, mc68hc08az60 Datasheet - Page 127

• Manufacturer Part Number: mc68hc08az60
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

23-cgm
MOTOROLA
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5% acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz 50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is
operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time
is the time taken to return from 900 kHz to 1 MHz 5 kHz. Five kHz = 5%
of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
Freescale Semiconductor, Inc.
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For More Information On This Product,
Acquisition time, t
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance,
Acquisition time is based on an initial frequency error,
(f
control mode (see
Modes
becomes set in the PLL bandwidth control register (PBWC).
Lock time, t
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance,
time is based on an initial frequency error, (f
more than 100%. In automatic bandwidth control mode, lock time
expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See
Bandwidth Modes
des
Clock Generator Module (CGM)
– f
Go to: www.freescale.com
orig
on page 111), acquisition time expires when the ACQ bit
)/f
Lock
des
, of not more than 100%. In automatic bandwidth
, is the time the PLL takes to reduce the error
acq
Manual and Automatic PLL Bandwidth
on page 111).
, is the time the PLL takes to reduce the error
Manual and Automatic PLL
Acquisition/Lock Time Specifications
Clock Generator Module (CGM)
MC68HC08AZ60 — Rev 1.0
des
– f
orig
)/f
Lock
des
, of not
. Lock
trk
.
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