mc68hc08az60 Freescale Semiconductor, Inc, mc68hc08az60 Datasheet - Page 154

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mc68hc08az60

Manufacturer Part Number
mc68hc08az60
Description
M68hc08 Family Of 8-bit Microcontroller Units Mcus
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Computer Operating Properly Module (COP)
Functional Description
MC68HC08AZ60 — Rev 1.0
154
NOTE:
NOTE:
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler. If not cleared by software, the COP counter overflows and
generates an asynchronous reset after 2
cycles, depending on the state of the COP long timeout bit, COPL, in the
CONFIG-1. When COPL = 1, a 4.9152-MHz crystal gives a COP timeout
period of 53.3 ms. Writing any value to location $FFFF before an
overflow occurs prevents a COP reset by clearing the COP counter and
stages 4–12 of the SIM counter.
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is
held at V
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
Freescale Semiconductor, Inc.
For More Information On This Product,
Computer Operating Properly Module (COP)
Hi
. During the break state, V
Go to: www.freescale.com
Hi
on the RST pin disables the COP.
13
– 2
4
or 2
18
– 2
4
CGMXCLK
MOTOROLA
2-cop

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