mc68hc08az60 Freescale Semiconductor, Inc, mc68hc08az60 Datasheet - Page 290

• Manufacturer Part Number: mc68hc08az60
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

I/O Ports
Data Direction
Register D
MC68HC08AZ60 — Rev 1.0
290
NOTE:
Address:
DDRD bits always determine whether reading port D returns the states
of the latches or logic 0.
TACLK/TBCLK — Timer Clock Input Bit
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 13
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
The PTD6/TACLK pin is the external clock input for the TIMA. The
PTD4/TBLCK pin is the external clock input for the TIMB. The
prescaler select bits, PS[2:0], select PTD6/TACLK or PTD4/TBLCK
as the TIM clock input. (See
Registers
Registers
PTD6/TACLK
While TACLK/TBCLK are selected corresponding DDRD bits have no
effect.
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
For More Information On This Product,
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
DDRD7
$0007
Bit 7
0
shows the port D I/O logic.
Figure 12. Data Direction Register D (DDRD)
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on page 384 and
on page 262). When not selected as the TIM clock,
DDRD6
and
6
0
I/O Ports
PTD4/TBLCK are available for general-purpose I/O.
DDRD5
5
0
TIMB Channel Status and Control
TIMA Channel Status and Control
DDRD4
4
0
DDRD3
3
0
DDRD2
2
0
DDRD1
1
0
MOTOROLA
DDRD0
12-ioports
Bit 0
0