mc68hc08az60 Freescale Semiconductor, Inc, mc68hc08az60 Datasheet - Page 91

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mc68hc08az60

Manufacturer Part Number
mc68hc08az60
Description
M68hc08 Family Of 8-bit Microcontroller Units Mcus
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Computer
Operating
Properly (COP)
Reset
Illegal Opcode
Reset
9-sim
MOTOROLA
CGMXCLK
CGMOUT
PORRST
OSC1
RST
IAB
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
CONFIG-1 register is at logic zero.
See
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the MOR register is logic zero, the SIM
treats the STOP instruction as an illegal opcode and causes an illegal
opcode reset.
CYCLES
Freescale Semiconductor, Inc.
4096
Computer Operating Properly Module (COP)
For More Information On This Product,
System Integration Module (SIM)
Figure 7. POR Recovery
CYCLES
Go to: www.freescale.com
32
CYCLES
32
$FFFE
System Integration Module (SIM)
Reset and System Initialization
MC68HC08AZ60 — Rev 1.0
on page 153.
$FFFF
91

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