isp1583 NXP Semiconductors, isp1583 Datasheet - Page 25
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isp1583
Manufacturer Part Number
isp1583
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1583.pdf
(100 pages)
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NXP Semiconductors
ISP1583_6
Product data sheet
7.17.1 Power-sharing mode
[2]
As can be seen in
the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V
supplied through the power source of the system. When the USB cable is plugged in, the
ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled.
The processor will experience continuous interrupt because the default status of the
interrupt pin when operating in sharing mode with V
this, implement external V
be connected to pin GPIO of the processor to qualify the interrupt from the ISP1583.
Remark: When the core power is applied, the ISP1583 must be reset using the RESET_N
pin. The minimum width of the reset pulse width must be 2 ms.
Fig 13. Power-sharing mode
Fig 14. Interrupt pin status during power off in power-sharing mode
V
CC(I/O)
V
CC(I/O)
can range from 1.65 V to 3.6 V. If the application is bus-powered, a voltage regulator must be used.
is system powered.
V
V
CC(3V3)
V
V
Figure
CC(I/O)
CC(3V3)
CC(I/O)
INT
ISP1583
Rev. 06 — 20 August 2007
to GPIO of processor
for sensing V
13, in power-sharing mode, V
BUS
power off
RPU
V
BUS
sensing circuitry. The output from the voltage regulator can
1.5 k
BUS
REGULATOR
5 V-to-3.3 V
VOLTAGE
Hi-Speed USB Peripheral Controller
BUS
power off
CC(3V3)
not present is LOW. To overcome
V
1 µF
BUS
is supplied by the output of
004aaa459
1 M
BUS
© NXP B.V. 2007. All rights reserved.
USB
004aaa458
ISP1583
. V
CC(I/O)
25 of 100
is