isp1583 NXP Semiconductors, isp1583 Datasheet - Page 74
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isp1583
Manufacturer Part Number
isp1583
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1583.pdf
(100 pages)
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NXP Semiconductors
Table 102. ISP1583 register access timing parameters: multiplexed address/data bus
V
ISP1583_6
Product data sheet
Symbol
Reading
t
t
t
t
t
Writing
t
t
t
t
t
General
T
t
RLRH
RLDV
RHDZ
RHSH
LLRL
WLWH
DVWH
LLWL
WHDZ
WHSH
AVLL
CC(I/O)
cy(RW)
= 1.65 V to 3.6 V; V
12.1.2.1 ALE function
12.1.2 Split bus mode
Parameter
RW_N/RD_N LOW pulse width
RW_N/RD_N LOW to data valid delay
RW_N/RD_N HIGH to data outputs 3-state delay
RW_N/RD_N HIGH to CS_N HIGH delay
ALE/A0 LOW set-up time before RW_N/RD_N LOW
DS_N/WR_N LOW pulse width
data set-up time before DS_N/WR_N HIGH
ALE/A0 LOW to DS_N/WR_N LOW delay
data hold time after DS_N/WR_N HIGH
DS_N/WR_N HIGH to CS_N HIGH delay
read or write cycle time
address set-up time before ALE/A0 LOW
8051 mode
Fig 25. EOT timing in generic processor mode
•
•
CC(3V3)
BUS_CONF/DA0 = LOW: split bus mode
MODE1 = LOW: ALE function
– MODE0/DA1 = HIGH: 8051 mode; see
(1) Programmable polarity: shown as active LOW.
Remark: EOT must be valid for 36 ns (minimum) when pins RW_N/RD_N and DS_N/WR_N
are active.
= 3.3 V; V
RW_N/RD_N or
DS_N/WR_N
GND
EOT
= 0 V; T
DREQ
Rev. 06 — 20 August 2007
(1)
amb
= 40 C to +85 C.
Conditions
36 ns (min)
t
h1
Table 2
Hi-Speed USB Peripheral Controller
Min
> t
-
0
0
0
15
5
0
5
0
80
0
RLDV
Typ
-
-
-
-
-
-
-
-
-
-
-
-
004aaa378
© NXP B.V. 2007. All rights reserved.
ISP1583
Max
-
25
15
-
-
-
-
-
-
-
-
-
74 of 100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns