isp1583 NXP Semiconductors, isp1583 Datasheet - Page 65
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isp1583
Manufacturer Part Number
isp1583
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1583.pdf
(100 pages)
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NXP Semiconductors
ISP1583_6
Product data sheet
Table 91.
Bit
7
6 to 5
4
3
2
1
0
Symbol
FORCEHS
-
FORCEFS
PRBS
KSTATE
JSTATE
SE0_NAK
Test Mode register: bit description
Description
Force High-Speed: Logic 1 forces the hardware to high-speed mode only
and disables the chirp detection logic.
reserved
Force Full-Speed: Logic 1 forces the physical layer to full-speed mode only
and disables the chirp detection logic.
Predetermined Random Pattern: Logic 1 sets the DP and DM pins to
toggle in a predetermined random pattern.
K-State: Logic 1 sets the DP and DM pins to the K state.
J-State: Logic 1 sets the DP and DM pins to the J state.
SE0 NAK: Logic 1 sets the DP and DM pins to a high-speed quiescent
state. The device only responds to a valid high-speed IN token with a NAK.
Rev. 06 — 20 August 2007
Hi-Speed USB Peripheral Controller
© NXP B.V. 2007. All rights reserved.
ISP1583
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