isp1583 NXP Semiconductors, isp1583 Datasheet - Page 4
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isp1583
Manufacturer Part Number
isp1583
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1583.pdf
(100 pages)
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Fig 1. Block diagram
RESET_N
1.5 k
V
12 k
(1) Pin 15 is shared by READY and IORDY.
(2) Pin 60 is shared by MODE0 and DA1.
(3) Pin 62 is shared by BUS_CONF and DA0.
CC(3V3)
3.3 V
The figure shows the ISP1583BS pinout. For the ISP1583ET and ISP1583ET1 ballouts, see
The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration
register).
RREF
RPU
13, 35, 59
61
2
6
7
DGND
REGULATORS
to or from USB
HI-SPEED USB
TRANSCEIVER
POWER-ON
VOLTAGE
DP
RESET
AGND
3
DM
4
1, 5
SoftConnect
VCC1V8
1.8 V
32, 56
internal
reset
analog
supply
digital
supply
V
BUS
55
SUSPEND WAKEUP
CONTROLLER
SYSTEM
64
SIE/PIE
XTAL1
12 MHz
58
NXP
63
XTAL2
57
MANAGEMENT
INTEGRATED
MEMORY
RAM (8 kB)
UNIT
I/O pad supply
V
ISP1583
CC(I/O)
26, 41, 54
CONTROLLER
REGISTERS
HANDLER
OTG SRP
HANDLER
MODULE
MICRO-
DMA
DMA
Table
CS0_N
2.
CS1_N
21
22
DA0
MICROCONTROLLER
DMA INTERFACE
62
DA1
(3)
INTERFACE
60
(2)
DA2
17
DREQ
DACK
9
10 11 12
DIOR
DIOW
37 to 40,
004aaa268
42 to 53
23 to 25,
27 to 31
14
15
18
62
60
34
36
19
20
15
16
8
16
8
EOT
INTRQ
IORDY
DATA[15:0]
BUS_CONF
MODE0
MODE1
AD[7:0]
CS_N
ALE/A0
RW_N/RD_N
DS_N/WR_N
READY
INT
(1)
(2)
(1)
(3)