isp1582 NXP Semiconductors, isp1582 Datasheet - Page 41

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 50.
ISP1582_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
DMA Hardware register: bit allocation
8.4.4 DMA Hardware register (address: 3Ch)
R/W
7
0
0
ENDIAN[1:0]
Table 49.
[1]
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
This register determines the polarity of bus control signals (EOT, DACK, DREQ, DIOR and
DIOW). It also controls whether the upper and lower parts of the data bus are swapped
(bits ENDIAN[1:0]).
Table 51.
Bit
3 to 2
1
0
Bit
7 to 6 ENDIAN[1:0]
5
4
The DREQ pin will be driven only after performing a write access to the DMA Configuration register (that is,
after configuring the DMA Configuration register).
R/W
Symbol
EOT_POL
-
6
0
0
Symbol
MODE[1:0]
-
WIDTH
DMA Configuration register: bit description
DMA Hardware register: bit description
EOT_POL
R/W
5
0
0
Rev. 06 — 20 September 2007
Description
Endian: These bits determine whether the data bus is swapped between
the internal RAM and the DMA bus.
00 — Normal data representation; 16-bit bus: MSByte on DATA[15:8],
LSByte on DATA[7:0]
01 — Swapped data representation; 16-bit bus: MSByte on DATA[7:0],
LSByte on DATA[15:8]
10 — reserved
11 — reserved
Remark: While operating with the 8-bit data bus, bits ENDIAN[1:0] must
always be set to 00b.
EOT Polarity: Selects the polarity of the End-Of-Transfer input.
0 — EOT is active LOW
1 — EOT is active HIGH
reserved; must be set to logic 0.
Description
Mode: These bits affect GDMA handshake signals.
00 — DIOW strobes data from the DMA bus into the ISP1582; DIOR
puts data from the ISP1582 on the DMA bus.
01 — DACK strobes data from the DMA bus into the ISP1582; DIOR
puts data from the ISP1582 on the DMA bus.
10 — DACK strobes data from the DMA bus into the ISP1582 and
also puts data from the ISP1582 on the DMA bus.
11 — reserved
reserved
Width: This bit selects the DMA bus width.
0 — 8-bit data bus
1 — 16-bit data bus
reserved
4
-
-
-
[1]
ACK_POL
R/W
3
0
0
Hi-Speed USB Peripheral Controller
…continued
DREQ_
POL
R/W
2
1
1
WRITE_
POL
R/W
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1582
Table
READ_
POL
R/W
0
0
0
41 of 69
50.