isp1582 NXP Semiconductors, isp1582 Datasheet - Page 8

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Functional description
ISP1582_6
Product data sheet
7.1 DMA interface, DMA handler and DMA registers
The ISP1582 is a high-speed USB Peripheral Controller. It implements the Hi-Speed USB
or the Original USB physical layer and the packet protocol layer. It concurrently maintains
up to 16 USB endpoints (control IN, control OUT, and seven IN and seven OUT
configurable) along with endpoint EP0 setup, which accesses the set-up buffer. The
“Universal Serial Bus Specification Rev.
using the external firmware.
For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer
data to or from external memory or devices. The DMA interface can be configured by
writing to proper DMA registers (see
The ISP1582 supports Hi-Speed USB and Original USB signaling. The USB signaling
speed is automatically detected.
The ISP1582 has 8 kB of internal FIFO memory, which is shared among enabled USB
endpoints, including control IN and control OUT endpoints, and set-up token buffer.
There are seven IN and seven OUT configurable endpoints, and two fixed control
endpoints that are 64 bytes long. Any of the seven IN and seven OUT endpoints can be
separately enabled or disabled. The endpoint type (interrupt, isochronous or bulk) and
packet size of these endpoints can be individually configured, depending on the
requirements of the application. Optional double buffering increases the data throughput
of these data endpoints.
The ISP1582 requires 3.3 V power supply. It has 5 V tolerant I/O pads and an internal
1.8 V regulator to power the digital logic.
The ISP1582 operates on a 12 MHz crystal oscillator. An integrated 40
multiplier generates the internal sampling clock of 480 MHz.
The DMA block can be subdivided into two blocks: DMA handler and DMA interface.
The firmware writes to the DMA Command register to start a DMA transfer (see
The handler interfaces to the same FIFO (internal RAM) as used by the USB core. On
receiving the DMA command, the DMA handler directs the data from the endpoint FIFO to
the external DMA device or from the external DMA device to the endpoint FIFO.
The DMA interface configures the timing and the DMA handshake. Data can be
transferred using either the DIOR and DIOW strobes or by the DACK and DREQ
handshakes. DMA configurations are set up by writing to the DMA Configuration register
(see
Remark: The DMA endpoint buffer length must be a multiple of 4 bytes.
For details on DMA registers, see
Table 48
and
Table
Rev. 06 — 20 September 2007
49).
Section
Section
2.0”, Chapter 9 protocol handling is executed
8.4.
8.4).
Hi-Speed USB Peripheral Controller
© NXP B.V. 2007. All rights reserved.
ISP1582
PLL clock
Table
Ref. 1
8 of 69
43).