lan9313 Standard Microsystems Corp., lan9313 Datasheet - Page 226
lan9313
Manufacturer Part Number
lan9313
Description
Lan9313/lan9313i Three Port 10/100 Managed Ethernet Switch With Mii
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LAN9313.pdf
(398 pages)
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Revision 1.2 (04-08-08)
13.1.8.3
31:28
BITS
24:0
27
26
25
RESERVED
Device Ready (READY)
When set, this bit indicates that the LAN9313/LAN9313i is ready to be
accessed. Upon power-up, nRST reset, or digital reset, the host processor
may interrogate this field as an indication that the LAN9313/LAN9313i has
stabilized and is fully active.
This bit can cause an interrupt if enabled.
Note:
AMDIX_EN Strap State Port 2
This bit reflects the state of the auto_mdix_strap_2 strap that connects to
the PHY. The strap value is loaded with the level of the auto_mdix_strap_2
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by bit 15 and 13 of the Port 2 PHY Special Control/Status
Indication Register
AMDIX_EN Strap State Port 1
This bit reflects the state of the auto_mdix_strap_1 strap that connects to
the PHY. The strap value is loaded with the level of the auto_mdix_strap_1
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by bit 15 and 13 of the Port 1 PHY Special Control/Status
Indication Register
RESERVED
Hardware Configuration Register (HW_CFG)
This register allows the configuration of various hardware features.
Note: This register can be polled while the LAN9313/LAN9313i is in the reset or not ready state
Note: In SMI mode, either half of this register can be read without the need to read the other half.
Note 13.49 The default value of this field is determined by the configuration strap auto_mdix_strap_2.
Note 13.50 The default value of this field is determined by the configuration strap auto_mdix_strap_1.
With the exception of the HW_CFG, BYTE_TEST, and
RESET_CTL registers, read access to any internal resources is
forbidden while the READY bit is cleared. Writes to any address
are invalid until this bit is set.
(READY bit is cleared). Returned data will be invalid during the reset state since the serial
interfaces are also in reset at this time.
Offset:
See
See
(Section
(Section
Section 4.2.4, "Configuration Straps," on page 45
Section 4.2.4, "Configuration Straps," on page 45
13.2.2.10).
13.2.2.10).
074h
DESCRIPTION
DATASHEET
226
Size:
Three Port 10/100 Managed Ethernet Switch with MII
32 bits
for more information.
for more information.
TYPE
SMSC LAN9313/LAN9313i
RO
RO
RO
RO
RO
Note 13.49
Note 13.50
DEFAULT
Datasheet
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