lan9313 Standard Microsystems Corp., lan9313 Datasheet - Page 231

• Manufacturer Part Number: lan9313
• Description: Lan9313/lan9313i Three Port 10/100 Managed Ethernet Switch With Mii
• Manufacturer: Standard Microsystems Corp.

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
13.2
13.2.1
13.2.2
INDEX #
0
1
2
3
4
5
This section details the various LAN9313/LAN9313i Ethernet PHY control and status registers. The
LAN9313/LAN9313i contains three PHY’s: Port 1 PHY, Port 2 PHY and a Virtual PHY. All PHY registers
follow the IEEE 802.3 (clause 22.2.4) specified MII management register set. All functionality and bit
definitions comply with these standards. The IEEE 802.3 specified register index (in decimal) is
included with each register definition, allowing for addressing of these registers via the MII serial
management protocol. For additional information on the MII management protocol, refer to the IEEE
802.3 Specification.
Each individual PHY is assigned a unique PHY address as detailed in
Addressing," on page
Virtual PHY Registers
The Virtual PHY provides a basic MII management interface for communication with an standard
external MAC as if it was attached to a single port PHY. The Virtual PHY registers differ from the Port
1 & 2 PHY registers in that they are addressable via the memory map, as described in
well as serially. These modes of access are described in
Because the Virtual PHY registers are also memory mapped, their definitions have been included in
the
PHY MII addressable registers and their corresponding register index numbers is also included in
Table
Note: When serially accessed, the Virtual PHY registers are only 16-bits wide, as is standard for MII
Port 1 & 2 PHY Registers
The Port 1 and Port 2 PHY’s are comparable in functionality and have an identical set of non-memory
mapped registers. The Port 1 and Port 2 PHY registers are not memory mapped. These registers are
indirectly accessed through the
Management Interface Data Register (PMI_DATA)
modes only) or through the MII management pins (in MAC or PHY SMI managed modes only) via the
MII serial management protocol specified in IEEE 802.3 clause 22. See
Operation," on page 23
2 PHY registers are functionally identical, their register descriptions have been consolidated. A
lowercase “x” has been appended to the end of each PHY register name in this section, where “x”
should be replaced with “1” or “2” for the Port 1 PHY or the Port 2 PHY registers respectively. A list
of the Port 1 & 2 PHY MII addressable registers and their corresponding register index numbers is
included in
7.1.1, "PHY Addressing," on page
Ethernet PHY Control and Status Registers
System Control and Status Registers Section 13.1.7, "Virtual PHY," on page
PHY_BASIC_CONTROL_x
13.4.
PHY_AN_LP_BASE_ABILITY_x
PHY_BASIC_STATUS_x
management of PHY’s.
PHY_AN_ADV_x
PHY_ID_MSB_x
PHY_ID_LSB_x
Table
Table 13.7 Port 1 & 2 PHY MII Serially Adressable Registers
SYMBOL
13.7. Each individual PHY is assigned a unique PHY address as detailed in
84.
for a details on the various LAN9313/LAN9313i modes. Because the Port 1 &
PHY Management Interface Access Register (PMI_ACCESS)
84.
DATASHEET
Port x PHY Basic Control Register,
Port x PHY Basic Status Register,
Port x PHY Identification MSB Register,
Port x PHY Identification LSB Register,
Port x PHY Auto-Negotiation Advertisement Register,
Section 13.2.2.5
Port x PHY Auto-Negotiation Link Partner Base Page Ability
Register,
231
Section 13.2.2.6
registers (in MAC or PHY I
Section 13.1.7, "Virtual PHY," on page
REGISTER NAME
Section 13.2.2.2
Section 13.2.2.1
Section 13.2.2.4
Section 2.3, "Modes of
Section 13.2.2.3
209. A list of the Virtual
2
Section 7.1.1, "PHY
C and SPI managed
Revision 1.2 (04-08-08)
Table
and
13.1, as
Section
209.
PHY