lan9313 Standard Microsystems Corp., lan9313 Datasheet - Page 55

• Manufacturer Part Number: lan9313
• Description: Lan9313/lan9313i Three Port 10/100 Managed Ethernet Switch With Mii
• Manufacturer: Standard Microsystems Corp.

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
5.2.3
5.2.4
5.2.5
Ethernet PHY Interrupts
The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The top-level PHY_INT1
(bit 26) and PHY_INT2 (bit 27) of the
P H Y i n t e r r u p t e v e n t o c c u r r e d i n t h e
(PHY_INTERRUPT_SOURCE_x).
Port 1 and Port 2 PHY interrupts are enabled/disabled via their respective
Register
via the
Port 2 PHYs are each capable of generating unique interrupts based on the following events:
In order for a Port 1 or Port 2 interrupt event to trigger the external IRQ interrupt pin, the desired PHY
interrupt event must be enabled in the corresponding
(PHY_INTERRUPT_MASK_x), the PHY_INT1(Port 1 PHY) and/or PHY_INT2(Port 2 PHY) bits of the
Interrupt Enable Register (INT_EN)
of the
For additional details on the Ethernet PHY interrupts, refer to
page
GPIO Interrupts
Each GPIO[11:0] of the LAN9313/LAN9313i is provided with its own interrupt. The top-level GPIO (bit
12) of the
in the
Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
and status of each GPIO[11:0] interrupt.
In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt
must be enabled in the
(GPIO_INT_STS_EN), bit 12 (GPIO_EN) of the
IRQ output must be enabled via bit 8 (IRQ_EN) of the
For additional details on the GPIO interrupts, refer to
General Purpose Timer Interrupt
A General Purpose Timer (GPT) interrupt is provided in the top-level
(INT_STS)
Purpose Timer Configuration Register (GPT_CFG)
19 of the
In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT
must be enabled via the bit 29 (TIMER_EN) in the
(GPT_CFG), bit 19 of the
enabled via bit 8 (IRQ_EN) of the
For additional details on the General Purpose Timer, refer to
on page
ENERGYON Activated
Auto-Negotiation Complete
Remote Fault Detected
Link Down (Link Status Negated)
Auto-Negotiation LP Acknowledge
Parallel Detection Fault
Auto-Negotiation Page Received
96.
Interrupt Configuration Register
General Purpose I/O Interrupt Status and Enable Register
Port x PHY Interrupt Source Flags Register
141.
(PHY_INTERRUPT_MASK_x). The source of a PHY interrupt can be determined and cleared
Interrupt Status Register (INT_STS)
Interrupt Status Register (INT_STS)
and
Interrupt Enable Register (INT_EN)
Interrupt Enable Register (INT_EN)
General Purpose I/O Interrupt Stat us and Enable Regist er
Interrupt Configuration Register
DATASHEET
must be set, and IRQ output must be enabled via bit 8 (IRQ_EN)
(IRQ_CFG).
Interrupt Status Register (INT_STS)
55
provides indication that a GPIO interrupt event occurred
P o r t x P H Y I n t e r r u p t S o u r c e F l a g s R e g i s t e r
is written with 1.
Interrupt Enable Register (INT_EN)
wraps past zero to FFFFh, and is cleared when bit
(bit 19). This interrupt is issued when the
(PHY_INTERRUPT_SOURCE_x). The Port 1 and
Section 12.2.2, "GPIO Interrupts," on page
General Purpose Timer Configuration Register
Interrupt Configuration Register
Port x PHY Interrupt Mask Register
Section 11.1, "General Purpose Timer,"
must be set, and IRQ output must be
Section 7.2.8.1, "PHY Interrupts," on
(GPIO_INT_STS_EN). The
(IRQ_CFG).
provides enabling/disabling
Port x PHY Interrupt Mask
Interrupt Status Register
provides indication that a
Revision 1.2 (04-08-08)
must be set, and
(IRQ_CFG).
General
General
143.