lan9313 Standard Microsystems Corp., lan9313 Datasheet - Page 32

• Manufacturer Part Number: lan9313
• Description: Lan9313/lan9313i Three Port 10/100 Managed Ethernet Switch With Mii
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
PIN
10
12
15
60
11
Note 3.3
Management
Management
MII Receive
MII Receive
Data Valid
MII Port
Duplex
NAME
Clock
Clock
Data
MII
MII
When used as an output, the pin(s) input buffer(s) and pull-down(s) are disabled.
Table 3.4 LAN Port 0(External MII) Pins (continued)
MII_DUPLEX
SYMBOL
RXCLK
RXDV
MDIO
MDC
DATASHEET
BUFFER
Note 3.3
Note 3.3
Note 3.5
Note 3.6
Note 3.7
IS/O12
TYPE
IS/O8
IS/O8
IS/O8
(PD)
(PD)
(PU)
IS
32
MII Receive Data Valid: Indicates valid data on
RXD[3:0].
MII Receive Clock:
MII Management Data:
See
MII Management Clock:
See
MII Port Duplex: This pin sets the duplex of the
MII port. Its’ value can be changed at any time (live
value) and can be overridden by disabling the
Auto-Negotiation (VPHY_AN)
Basic Control Register (VPHY_BASIC_CTRL)
the Virtual PHY.
In MAC mode, this signal is typically tied to the
duplex indication from the external PHY.
In PHY mode, this signal is typically tied high or low
as needed.
The polarity of this signal depends upon the
duplex_pol_strap_mii strap. If duplex_pol_strap_mii
is 0, a MII_DULPEX value of 0 indicates full duplex,
and 1 indicates half duplex. If duplex_pol_strap_mii
is 1, a MII_DULPEX value of 1 indicates full duplex,
and 0 indicates half duplex.
In MAC mode, this signal is input from an
external PHY.
In PHY mode, this signal is output to an external
MAC. See
In MAC mode, this is the receiver clock input from
an external PHY.
In PHY mode, this is the receiver clock output to
an external MAC. See
In SMI/MII slave management modes, this signal
is the management data to/from an external
master.
In MII master management modes, this signal is
the management data to/from an external PHY.
In SMI/MII slave management modes, this is the
management clock input from an external master.
In MII master management modes, this is the
management clock output to an external PHY.
Note 3.5
Note
3.6.
Note
Three Port 10/100 Managed Ethernet Switch with MII
DESCRIPTION
3.3.
Note
SMSC LAN9313/LAN9313i
bit in the
3.3.
Virtual PHY
Datasheet
of