peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 112

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Register 2
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
EDMA
IPC(1:0)
Bit
7
0
Enable External DMA Support
This bit field controls the DMA operation mode:
EDMA=’0’
EDMA=’1’
Interrupt Pin Characteristic
These bits control the characteristic of interrupt output pin INT/INT:
IPC(1:0)
’00’
’01’
’10’
’11’
EDMA
GMODE
Global Mode Register
6
read/write
0B
01
written by CPU
evaluated by SEROCCO-H
H
H
The external DMA controller support functions are
disabled. SEROCCO-H is operated in standard register
access controlled mode.
External DMA controller support functions are enabled.
Output Function:
Open Drain active low
Push/Pull active low
Reserved.
Push/Pull active high
5
IPC(1:0)
DMA and Global Control
5-112
4
OSCPD
3
Register Description (GMODE)
2
0
DSHP
1
PEB 20525
PEF 20525
2000-09-14
GIM
0