peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 169

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
The following register bit fields allow flexible assignment of bit- or octet-aligned receive
time-slots to the serial channel. For more detailed information refer to chapters
Mode 5a (Time Slot Mode)” on Page 56
on Page
RCS(2:0)
REPCM
RTSN(6:0)
RCC(8:0)
63.
Receive Clock Shift
This bit field determines the receive clock shift.
Enable PCM Mask Receive
This bit selects the additional Receive PCM Mask (refer to register
PCMRX0..PCMRX3):
REPCM=’0’
REPCM=’1’
Receive Time Slot Number
This bit field selects the start position of the timeslot in time-slot
configuration mode (clock mode 5a/5b):
Offset = 1+RTSN*8 + RCS (1..1024 clocks)
Receive Channel Capacity
This bit field determines the receive time-slot width in standard time-slot
configuration (bit REPCM=’0’):
Number of bits = RCC + 1, (1..512 bits/time-slot)
Standard time-slot configuration.
The time-slot width is constant 8 bit, bit fields ’RTSN’ and
’RCS’ determine the offset of the PCM mask and ’RCC’ is
ignored. Each time-slot selected via register
PCMRX0..PCMRX3
5-169
and
“Clock Mode 5b (Octet Sync Mode)”
is an active receive timeslot.
Register Description (RTSA3)
PEB 20525
PEF 20525
2000-09-14
“Clock