peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 196

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
XMR
XPR
ALLS
Transmit Message Repeat
This bit is set to ’1’, if transmission of the last frame has to be repeated
(by software), because
• the SCC has received a negative acknowledge to an I-frame (in HDLC
• a collision occured after at least 14.5 bytes of data have been
• CTS signal was deasserted after at least 14.5bytes of data have been
Note: For easy recovery from a collision event (in bus configuration
Transmit Pool Ready Interrupt
This bit is set to ’1’, if a transmitter reset command was executed
successfully (command bit ’XRES’ in register CMDRL) and whenever
the XFIFO is able to accept new transmit data again.
An ’XPR’ interrupt is not generated, if no sufficient transmit clock is
available (depending on the selected clock mode).
ALL Sent Interrupt
This bit is set to ’1’:
• if the last bit of the current HDLC frame is sent out via pin TxD and no
• if an I-frame is sent out completely via pin TxD and either a valid
Automode operation);
completely sent out, i.e. automatic re-transmission cannot be
performed by the SCC;
completely sent out.
further frame is stored in the SCC transmit FIFO, i.e. the transmit FIFO
is empty (Address Mode 2/1/0);
acknowledge S-frame has been received or a time-out condition
occured because no valid acknowledge S-frame has been received in
time (Automode).
only), the SCC transmit FIFO should not contain more than one
complete frame. This can be achieved by using the ’ALLS’
interrupt to control the corresponding transmit channel forwarding
a new frame on all sent (ALLS) event only.
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Register Description (ISR2)
PEB 20525
PEF 20525
2000-09-14