peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 138

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
RMC
RNR
RSUC
RRES
Receive Message Complete
Self-clearing command bit:
RMC=’1’
Receiver Not Ready Command
NON self-clearing command bit:
This command bit is significant in HDLC Automode only.
RNR=’0’
RNR=’1’
Reset Signaling Unit Counter
Self-clearing command bit:
This command bit is significant if HDLC SS7 mode is selected.
RSUC=’1’
Receiver Reset Command
Self-clearing command bit:
RRES=’1’
With this bit the CPU indicates to SEROCCO-H that the
current receive data has been fetched out of the RFIFO.
Thus the corresponding space in the RFIFO can be
released and re-used by SEROCCO-H for further
incoming data.
Forces the receiver to enter its ’receiver-ready’ state. The
receiver acknowledges received poll or I-Frames with a
’receiver-ready’ indication.
Forces the receiver to enter its ’receiver-not-ready’ state.
The receiver acknowledges received poll or I-Frames with
a ’receiver-not-ready’ indication.
The Signaling System #7 (SS7) unit counter is reset.
The SCC receive FIFO is cleared and the receiver
protocol engines are reset to their initial state.
The SCC receive FIFO accepts new receive data from the
protocol engine immediately after receiver reset
procedure.
It is recommended to disable data reception before
issuing a receiver reset command by setting bit
CCR3L.RAC = ’0’ and enabling data reception afterwards.
A ’receiver reset’ command is recommended after all
changes in protocol mode configurations.
5-138
Register Description (CMDRH)
PEB 20525
PEF 20525
2000-09-14