peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 40

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Table 5
Pin No.
P-
LFBGA-
80-2
B2
C2
A2
A1
H8
D7
C9
Data Sheet
P-TQFP-
100-3
99
2
100
1
46
68
69
Test Interface Pins
Symbol In (I)
TRST
TCK
TDI
TDO
TMS
TEST1
TEST2
Out (O)
I
I
I
O
I
I
I
Function
JTAG Reset Pin (internal pull-up)
For proper device operation, a reset for the
boundary scan controller must be supplied to this
active low pin.
If the boundary scan of the SEROCCO-H is not
used, this pin can be connected to V
in reset state.
JTAG Test Clock (internal pull-up)
If the boundary scan of the SEROCCO-H is not
used, this pin may remain unconnected.
JTAG Test Data Input (internal pull-up)
If the boundary scan of the SEROCCO-H is not
used, this pin may remain unconnected.
JTAG Test Data Output
JTAG Test Mode Select (internal pull-up)
If the boundary scan of the SEROCCO-H is not
used, this pin may remain unconnected.
Test Input 1
When connected to V
in a vendor specific test mode.
This pin must be connected to V
Test Input 2
When connected to V
in a vendor specific test mode.
This pin must be connected to V
40
DD3
DD3
the SEROCCO-H works
the SEROCCO-H works
Pin Descriptions
SS
SS
.
.
SS
PEB 20525
PEF 20525
to keep it
2000-09-14