peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 144

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
CRL
C32
SOC(1:0)
SFLG
CRC Reset Value
This bit defines the initial value of the internal transmit/receive CRC
generators:
CRL=’0’
CRL=’1’
CRC 32 Select
This bit enables 32-bit CRC operation for transmit and receive.
C32=’0’
C32=’1’
Note: The internal ’valid frame’ criteria is updated depending on the
Serial Output Control
This bit field selects the RTS signal output function.
(This bit field is only valid in bus configuration modes selected via bit field
SC(2:0) in register CCR0H).
SOC = ’0X’
SOC = ’10’
SOC = ’11’
Shared Flags Transmission
This bit enables ’shared flag transmission’ in HDLC protocol mode. If
another transmit frame begin is stored in the SCC transmit FIFO, the
closing flag of the preceding frame becomes the opening flag of the next
frame (shared flags):
SFLG = ’0’
SFLG = ’1’
Note: The receiver always supports shared flags and shared zeros of
selected number of CRC-bytes.
consecutive flags.
Initial value is 0xFFFF
(32 bit CRC).
This is the default value for most HDLC/PPP applications.
Initial value is 0x0000
(32 bit CRC).
16-bit CRC-CCITT generation/checking.
32-bit CRC generation/checking.
RTS ouput signal is active during transmission of a frame
(active low).
RTS ouput signal is always inactive (high).
RTS ouput signal is active during reception of a frame
(active low).
Shared flag transmission disabled.
Shared flag transmission enabled.
5-144
H
H
(16 bit CRC), 0x00000000
(16 bit CRC), 0xFFFFFFFF
Register Description (CCR1H)
PEB 20525
PEF 20525
2000-09-14
H
H