peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 137

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
XRES
XF
XME
XREP
Transmitter Reset Command
Self-clearing command bit:
XRES=’1’
Transmit Frame
This self-clearing command bit is significant in interrupt driven operation
only (GMODE.EDMA=’0’).
XF=’1’
Transmit Message End
Self-clearing command bit:
XME=’1’
Transmission Repeat Command
Self-clearing command bit:
XREP=’1’
The SCC transmit FIFO is cleared and the transmitter
protocol engines are reset to their initial state.
A transmitter reset command is recommended after all
changes in protocol mode configurations (e.g. switching
between sub-modes of HDLC).
After having written up to 32 bytes to the XFIFO, this
command initiates transmission. In packet oriented
protocols like HDLC/PPP the opening flag is automatically
added by SEROCCO-H. If the end of the packet is part of
the transmit data, bit ’XME’ should be set in addition.
DMA Mode
After having written the length of the data block to be
transmitted to registers
initiates the data transfer from host memory to
SEROCCO-H by DMA. Transmission on the serial side
starts as soon as 32 bytes are transferred to the XFIFO or
the transmit byte counter value is reached.
Indicates that the data block written last to the XFIFO
contains the end of the packet. This bit should always be
set in conjunction with a transmit command (’XF’ or ’XIF’).
If bit ’XREP’ is set together with bit ’XME’ and ’XF’,
SEROCCO-H repeatedly transmits the contents of the
XFIFO (1..32 bytes).
The cyclic transmission can be stopped with the ’XRES’
command.
5-137
XBCL
Register Description (CMDRH)
and XBCH, this command
PEB 20525
PEF 20525
2000-09-14