peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 201

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Register 78
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
The Receive Status Byte ’RSTA’ contains comprehensive status information about the
last received frame (HDLC/PPP).
The SCC attaches this status byte to the receive data and thus it should be read from
the RFIFO.
In HDLC/PPP modes the RSTA value can optionally be read from this register address.
In extended transparent mode this status field does not apply.
Bit
VFR
7
RSTA
Receive Status Byte
RDO
6
read only
00
Channel A
58
written by SEROCCO-H to RFIFO;
read from RFIFO and evaluated by CPU
H
H
CRCOK
5
Channel B
A8
Receive Status Byte
H
RAB
5-201
4
3
HA(1:0)/
SU(1:0)
Register Description (RSTA)
2
C/R
1
PEB 20525
PEF 20525
2000-09-14
LA
0