peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 133

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
CD
RLI
DPLA
WFA
CD (Carrier Detect) Input Signal State
CD=’0’
CD=’1’
Note: Optionally this input can be programmed to generate an interrupt
Receive Line Inactive
This bit indicates that neither flags as interframe time fill nor data are
being received via the receive line.
RLI=’0’
RLI=’1’
Note: A receive clock must be provided in order to detect the receive line
DPLL Asynchronous
This bit is only valid if the receive clock is recovered by the DPLL and
FM0, FM1 or Manchester data encoding is selected. It is set when the
DPLL has lost synchronization. In this case reception is disabled
(receive abort condition) until synchronization has been regained. In
addition transmission is interrupted in all cases where transmit clock is
derived from the DPLL (clock mode 3a, 7a). Interruption of transmission
is performed the same way as on deactivation of the CTS signal.
DPLA=’0’
DPLA=’1’
Wait For Acknowledgement
This status bit is significant in Automode only. It indicates whether the
Automode state machine expects an acknowledging I- or S-Frame for a
previously sent I-Frame.
WFA=’0’
WFA=’1’
on signal level changes.
state.
CD input signal is low.
CD input signal is high.
Receive line is active, no constant high level is detected.
Receive line is inactive, i.e. more than 7 consecutive ’1’
are detected on the line.
DPLL is synchronized.
DPLL is asynchronous (re-synchronization process is
started automatically).
No acknowledge I/S-Frame is expected.
The Automode state machine is waiting for an
achnowledging S- or I-Frame.
5-133
Register Description (STARH)
PEB 20525
PEF 20525
2000-09-14