aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 134

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
LIN Hardware Synchronization Control Register 0:
Name:
Address:
Default Value:
Access:
Function:
Table 87. LHSCON0 MMR Bit Descriptions
Bit
31-13
12
11
10
9
8
Break Timer Compare Interrupt Disable:
Description
Reserved
These bits are reserved for future and should be written as 0 by user software.
Rising edge Detected Interrupt Disable
BSD Mode:
This bit is set to 1 to disable the Rising edge Detected interrupt.
This bit is cleared to 0 to enable the Break Rising edge Detected Interrupt
LIN Mode:
This bit is set to 1 to enable the Rising edge Detected interrupt.
This bit is cleared to 0 to disable the Break Rising edge Detected Interrupt
This bit is set to 1 to disable the Break Timer Compare interrupt.
This bit is cleared to 0 to enable the Break Timer Compare Interrupt
Break Timer Error Interrupt Disable:
This bit is set to 1 to disable the Break Timer Error interrupt.
This bit is cleared to 0 to enable the Break Timer Error Interrupt
LIN Transceiver, Stand-Alone Test Mode
This bit is cleared to 0 by user code to operate the LIN in normal mode, driven directly from the on-chip UART.
This bit is set to 1 by user code to enable external GPIO_7 and GPIO_8 pins to drive the LIN transceiver TxD and RxD respectively,
independent of the UART. The functions of GPIO_7 and GPIO_8 should first be configured by user code via GPIO function select
bits <0 and 4> in the GP2CON register.
Gate UART/BSD R/ W Bit
In LIN Mode (LHSCON0[6] is cleared to 0):
This bit is set to 1 by user code to disable the internal UART RxD (receive data) by gating it high until both the break field and
subsequent LIN Sync byte have been detected. This ensures the UART will not receive any spurious serial data during Break or
Sync field periods which will have to be flushed out of the UART before valid data fields can start to be received.
This bit is set to 0 by user code to enable the internal UART RxD (receive data) after the break field and subsequent LIN Sync byte
have been detected so that the UART can receive the subsequent LIN data fields.
In BSD Mode (LHSCON0<6> is set to1):
In BSD Read-Mode, this bit is set to 1 by user code to enable the generation of a Break Condition interrupt (LHSSTA[0]) on a
rising edge of the BSD bus. In BSD read mode the Break Timer (LHSVAL1) starts counting on the falling edge and stops counting
on the rising edge. The generate of an interrupt on this rising edge allows user code determine if a 0, 1 or Sync pulse width has
been received. It should also be noted that the Break timer will also still generate an interrupt if the value in the LIN Break
timer(LHSVAL1 read value) = the Break timer compare value (LHSVAL1 write value) and if the Break timer overflows. This
configuration can be used in BSD read mode detect fault conditions on the BSD bus.
In BSD Write Mode, this bit is cleared to 0 by user code to disable the generation of Break Condition interrupts on a rising edge
of the BSD bus (as is required in BSD Read mode).In BSD Write Mode, the LHS Compare Interrupt (LHSSTA[3]) is used to
determine when the MCU should release the BSD bus when transmitting data. If the Break Condition interrupt was still enabled
it would generate an unwanted interrupt as soon as the BSD bus is de-asserted. As in BSD Read Mode, the Break timer will stop
counting on a rising edge so the Break timer can also be used in this mode to allow user code confirm the pulse width in
transmitted data bits.
Note: Because of the finite propagation delay in the BSD transmit (from MCU to external pin) and receive (from external pin to
MCU) paths, user code must not switch between BSD Write and Read modes until the MCU confirms the external BSD pin is de-
asserted. Failure to adhere to this recommendation may result in the generation of an inadvertent Break Condition interrupt
Read/Write
LHSCON0
0xFFFF0784
0x00000000
The LHS Control register is a 32-bit register that in conjunction with the LHSCON1 register is used to configure the
LIN mode of operation
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Preliminary Technical Data