aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 32

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
In Summary, there are three levels of protection:
1.
2.
3.
Sequence to Write the Key and Set Permanent Protection
1.
2.
3.
4.
To remove or modify the protection the same sequence can be
used with a modified value of FEE0PRO.
The sequence above is illustrated in the following example, this
protects writing Page 4 and Page 5 of the Flash/EE:
Int a = FEE0STA;
FEE0PRO=0xFFFFFFFB;
FEE0ADR=0x66BB;
FEE0DAT=0xAA55;
FEE0MOD = 0x0048
FEE0CON= 0x0C;
while (FEE0STA & 0x04){}
protected.
31-16 ] and FEE0DAT [ Bits 15-0 ].
Temporary protection can be set and removed by writing
directly into FEE0HID MMR. This register is volatile and
therefore protection is only in place while the part remains
powered on. This protection is not reloaded after a power
cycle.
Keyed permanent protection can be set via FEE0PRO to
lock the protection configuration. The software key used at
the start of the required FEE0PRO write sequence is saved
once and must subsequently be used for any subsequent
access of the FEE0HID or FEE0PRO MMRs. A mass erase
sets the key back to 0xFFFF but also erases the entire user
code space.
Permanent Protection can be set via FEE0PRO, similarly to
Keyed Permanent Protection, the only difference been that
the software key used is 0xDEADDEAD. Once the
FEE0PRO write sequence is saved, only a mass erase sets
the key back to 0xFFFFFFFF. This also erases the entire
user code space.
Write in FEE0PRO corresponding to the pages to be
Write the new (user defined) 32 bit key in FEE0ADR [ Bits
Write 1,0 in FEE0MOD[6:5] and set FEE0MOD[3].
Run the write key command 0x0C in FEE0CON.
// Protect Pages 4 and 5
// Write key command
// Wait for command to finish
// Ensure FEE0STA is cleared
// 32 bit key value [Bits 31-16]
// 32 bit key value [Bits 15-0]
// Lock Security Sequence
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ADUC7033 FLASH/EE CONTROL INTERFACE
The access to and control of the Flash/EE memory on the
ADuC7033 is managed by an on-chip memory controller. The
controller manages the Flash/EE memory as two separate
blocks (0 and 1).
Block 0 consists of the 32 KB Flash/EE memory mapped from
0x00090000 to 0x00097FFF (including the 2 KB kernel space
which is reserved at the top of this block).
Block 1 consists of the 64 KB Flash/EE memory mapped from
0x0008 0000 to 0x0008 FFFF.
It should be noted that MCU core can continue to execute code
from one memory block while an active erase or program cycle
is being carried out on the other block. If a command operates
on the same block as the code currently executing, the core is
halted until the command is completed, this also applies to code
execution.
User Code, LIN and JTAG programming use the Flash/EE
Control Interface, which consists of the following MMRs :
FEExSTA (x= 0 or 1): read only register, reflects the status of the
Flash/EE Control Interface
FEExMOD (x= 0 or 1): sets the operating mode of the Flash/EE
Control Interface
FEExCON (x= 0 or 1): 8-bit command register. The commands
are interpreted as described in Table 13.
FEExDAT (x= 0 or 1): 16-bit data register.
FEExADR (x= 0 or 1): 16-bit address register.
FEExSIG (x= 0 or 1): Holds the 24-bit code signature as a result
of the signature command being initiated.
FEExHID (x= 0 or 1): Protection MMR. Controls read and
write protection of the Flash/EE memory code space. If
previously configured via the FEExPRO register, FEExHID may
require a software key to enable access.
FEExPRO (x= 0 or 1): A buffer of the FEExHID register, which
is used to store the FEExHID value, so it is automatically
downloaded to the FEExHID registers on subsequent reset and
power-on events.
NOTE: User Software must ensure that the Flash/EE
controller has completed any Erase or Write cycle before the
PLL is powered down. If the PLL is powered down before an
Erase or Write cycle is completed, the Flash/EE page or byte
may be corrupted.
The following sections describe in detail the bit designations of
each of Flash/EE control MMRs.
Preliminary Technical Data