aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 81

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It is used to service general purpose interrupt
handling of internal and external events.
The four 32-bit registers dedicated to IRQ are:
IRQSIG, reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in the
IRQSIG will be set, otherwise it is cleared. The IRQSIG bits are
cleared when the interrupt in the particular peripheral is
cleared. All IRQ sources can be masked in the IRQEN MMR.
IRQSIG is read-only.
IRQEN, provides the value of the current enable mask. When
bit is set to 1, the source request is enabled to create an IRQ
exception. When bit is set to 0, the source request is disabled or
masked which will not create an IRQ exception. IRQEN register
cannot be used to disable an interrupt.
IRQCLR, (write-only register) allows clearing the IRQEN
register in order to mask an interrupt source. Each bit set to 1
will clear the corresponding bit in the IRQEN register without
affecting the remaining bits. The pair of registers IRQEN and
IRQCLR allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
IRQSTA, (read-only register) provides the current enabled IRQ
source status (effectively a logic AND of the IRQSIG and
IRQEN bits). When set to 1 that source will generate an active
IRQ request to the ARM7TDMI core. There is no priority
encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ e d to create a single IRQ
signal to the ARM7TDMI core.
FIQ
The FIQ (Fast Interrupt reQuest) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface providing the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ, FIQSIG, FIQEN, FIQCLR and FIQSTA.
Bit 31 to 1 of FIQSTA are logically OR’ e d to create the FIQ
signal to the core and the bit 0 of both the FIQ and IRQ
registers (FIQ source).
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The logic for FIQEN and FIQCLR will not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to ‘1’
in FIQEN will, as a side effect, clear the same bit in IRQEN. A
bit set to ‘1’ in IRQEN will, as a side effect, clear the same bit in
FIQEN. An interrupt source can be disabled in both IRQEN
and FIQEN masks.
Programmed Interrupts
As the programmed interrupts are non-maskable, they are
controlled by another register, SWICFG, which write into both
IRQSTA and IRQSIG registers or/and FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 45. This MMR allows the control of
programmed source interrupt.
Table 45. SWICFG MMR Bit Descriptions
Bit
31-3
2
1
0
Note that any interrupt signal must be active for at least the
minimum interrupt latency time, to be detected by the interrupt
controller and to be detected by user in the IRQSTA/FIQSTA
register.
Description
Reserved
Programmed Interrupt-FIQ
Setting/clearing this bit correspond in setting/clearing
bit 1 of FIQSTA and FIQSIG
Programmed Interrupt-IRQ
Setting/clearing this bit correspond in setting/clearing
bit 1 of IRQSTA and IRQSIG
Reserved
FLASH/EE
PLL LOCK
FLASH/EE
PLL LOCK
LIN H/W
LIN H/W
TIMER0
TIMER1
TIMER2
TIMER3
TIMER0
TIMER1
TIMER2
TIMER3
UART
UART
XIRQ
XIRQ
ADC
ADC
SPI
SPI
Figure 29. Interrupt Structure
ADuC7030/ADuC7033
IRQ
FIQ