aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 68
aduc7030
Manufacturer Part Number
aduc7030
Description
Integrated Precision Battery Sensor For Automotive
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADUC7030.pdf
(150 pages)
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ADuC7030/ADuC7033
1.33KHz as is the improvement in stop-band rejection when
compared to the standard 1KHz response above.
In ADC Normal Power Mode, the maximum ADC throughput
rate is 8kHz which is configured by setting the SF and AF bits in
the ADCFLT MMR to 0, with all other filtering options
disabled. This results in 0x0000 written to ADCFLT and a
typical 8KHz filter response based on these settings is shown
below in Figure 21.
A modified version of the 8KHz filter response can be
configured by setting the ‘Running Average’ bit (ADCFLT[14]).
This has the effect of introducing an additional running average
by 2 filter on all ADC output samples. This further reduces the
ADC output noise and while maintaining an 8kHz ADC
through-put rate the ADC settling time is increased by 1 full
conversion period. The modified frequency response for this
configuration is shown below in Figure 22.
Figure 21. Typical Digital Filter Response at FADC=8 kHz, (ADCFLT = 0x0000)
Figure 20. ModifiedSinc3 Digital Filter Response at FADC=1.0kHz
–100
–100
–10
–20
–30
–40
–50
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–70
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–90
–10
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0
0
0
0
2k
500
4k
1000 1500 2000 2500 3000 3500 4000 4500 5000
6k
(ADCFLT = 0x0087)
8k
FREQUENCY (kHz)
FREQUENCY (kHz)
10k 12k 14k 16k 18k 20k 22k 24k
Rev. PrE | Page 68 of 150
At very low throughput rates, the chop bit in the ADCFLT
register can be enabled to minimize offset errors and more
importantly temperature drift in the ADC offset error. With
Chop enabled, there are again 2 primary variables (Sinc3
decimation factor and averaging factor) available to allow the
user select an optimum filter response trading off filter
bandwidth against ADC noise.
For example, with the CHOP bit ADCFLT[15] set to 1,
increasing the SF value (ADCFLT[6:0]) to 0x1F (31dec) and
selecting an AF value (ADCFLT[13:8]) of 0x16 (22dec) results
in an ADC through-put of 10Hz. The frequency response in
this case is shown in Figure 23.
Changing SF to 0x1D and setting AF to 0x3F, again with the
Chop bit enabled, configures the ADC into its minimum
through-put rate in Normal Mode of 4Hz. The digital filter
frequency response with this configuration is shown below in
Figure 24.
Figure 22. Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x4000)
Figure 23 Typical Digital Filter Response at FADC=8 kHz, (ADCFLT = 0x961F)
–100
–100
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–90
–10
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0
0
0
0
2k
20
Preliminary Technical Data
4k
40
6k
60
8k
FREQUENCY (kHz)
FREQUENCY (kHz)
80
10k 12k 14k 16k 18k 20k 22k 24k
100
120
140
160
180
200
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